[1] Chua LO, Yang L. Cellular neural networks: Theory. IEEE Transactions on Circuits and Systems. 1988;35(10):1257-1272

[2] Chua LO, Yang L. Cellular neural networks: Application. IEEE Transactions on Circuits and Systems. 1988;35:1273-1290

[3] Roska T, Chua LO, Wolf D, Kozek T, Tetzlaff R, Puffer F. Simulating nonlinear waves and partial differential equations via CNN—Part I: Basic techniques. IEEE Transactions on Circuits and Systems. 1995;42(10):807-815

[4] Thai VD, Cat PT. Modeling air pollution problem by cellular neural network. In: Proceeding (ISI) of 10th International Conference on Control, Automation, Robotics and Vision; Hanoi, Vietnam; 2008. pp. 1115-1118

[5] Thai VD, Cat PT. Solving two-dimensional Saint venant equation by using cellular neural network. In: Proceeding of the 7th Asian Control Conference—ASCC2009; Hong Kong; 2009. pp. 1258-1263

[6] Thai VD, Cat PT. Equivalence and stability of two-layer cellular neural network solving Saint venant 1D equation. In: Proceeding (ISI) of 11th International Conference on Control, Automation, Robotics and Vision (ICARCV2010); Singapore; 2010. pp. 704-709

[7] Thai VD, Anh BT, Duong VT. Develop some application of Cyclone—DE2C35 chip. Journal of Science and Technology - Thai Nguyen University. 2015;10(140):103-108

[8] Thai VD, Linh LH, Linh NM. Solving Navier-Stokes equation using FPGA cellular neural network chip. In: Proceeding of International Conference on Advances in Information and Communication Technology (ICTA2016). Springer Publishing; 2016. pp. 562-571

[9] Rusin WM. On solution to Navier-Stokes equation in critical spaces [Thesis of Doctor Philosophy]. 2010. Available from: http://conservancy.umn.edu/…/Rusin_umn_0130E_11277.pdf

[10] Hruska J. Intel launches Stratix 10: Altera FPGA combined with ARM CPU, 14nm manufacturing. Extremetech. 2016. Available from: https://www.extremetech.com/computing/237338-intel-launches-stratix-10-altera-fpga-combined-with-arm-cpu-14nm-manufacturing

[11] la Pedus M. Intel-Altera deal to shake up foundry landscape. Chip Design Magazine. 2013. Available from: http://chipdesignmag.com/display.php?articleId=5215

[12] Clive M. The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows. Elsevier; 2004. Available from: https://www.eu.elsevierhealth.com/about-us

[13] Clive M. Programmable Logic DesignLine. Xilinx Unveil Revolutionary 65nm FPGA Architecture: The Virtex-5 Family. 2006. Available from: https://www.eetimes.com/document.asp?doc_id=13001899

[14] David WP. Google patent search. Dynamic Data Reprogrammable PLA. 2009

[15] David WP, Peterson LR. Google patent search. Dynamic Data Reprogrammable PLA. 2009

[16] Wisniewski R. Synthesis of Compositional Microprogram Control Units for Programmable Devices. University of Zielona Góra Press; 2009, (ul. Podgórna 50, 65-246 Zielona Góra. Dane kontaktowe)

[17] Black F, Scholes MS. The pricing of options and corporate liabilities. Journal of Political Economy. 1973;81(3):59-637

[18] Chua LO, Roska T. Cellular Neural Networks and Visual Computing. Cambridge University Press; 2000. ISBN: 0-521-65247-2. Available from: https://en.wikipedia.org/wiki/Cambridge_University_Press

[19] FPGA Architecture for the Challenge. Available from: http://www.eecg.toronto.edu/∼vaughn/challenge/fpga_arch.html

[20] Intel® FPGAs offer a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built-in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power, and cost. Available from: https://www.intel.com/content/www/us/en/products/programmable/fpga.html